The present application relates to semiconductor technology. More particularly, the present application relates to a semiconductor structure, e.g., a dual damascene interconnect structure, that includes lower and upper interconnect levels that both contain binary metallization structures (i.e., first and second electrically conductive structures) embedded within an interconnect dielectric material layer present in the specific interconnect level. The present application also provides a method of forming such a structure.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring, i.e., interconnect, structures.
Within typical dual damascene interconnect structures, electrically conductive metal vias run perpendicular to the semiconductor substrate and electrically conductive metal lines run parallel to the semiconductor substrate. Typically, the electrically conductive metal vias are present beneath the electrically conductive metal lines and both features are embedded within an interconnect dielectric material layer.
In conventional dual damascene interconnect structures, copper or a copper containing alloy has been used as the material of the electrically conductive metal vias and lines. In recent years, advanced dual damascene interconnect structures containing a combined electrically conductive via/line feature have been developed in which an alternative metal such as cobalt or ruthenium is used as a liner in conjunction with, copper or a copper alloy. In such cases, copper voids are typically formed in the via and line portions of the damascene interconnect structure and the copper grain size is often small (less than 5 nm). Such advanced dual damascene interconnect structure may exhibit poor electromigration performance.
There is thus a need for providing advanced dual damascene interconnect structures including both copper and an alternative metal which exhibit void-free vias as well as void-free, large-grained copper lines.